- AMD announced EPYC 9006 'Venice' at Advancing AI 2026, aiming to advance server offerings in the agentic AI era.
- EPYC 9006 supports Gen2 MRDIMM-12800 and DDR5-8000 memory, eliminating Intel's MRDIMM advantage and improving AVX-512 with BMM.
- Venice offers up to 16-channel memory per socket, around 20% more performance per core over Turin, and up to 256 cores/512 threads per socket with Zen 6C.
- PCIe Gen 6 support with up to 160 lanes in dual socket, new power management features (FAST, UBPS, UPP), and top clock frequency of 5.0 GHz for the 96-core processor.
- The EPYC 9006 series includes SP7, SP8, and 9006X SP7 models (Venice-X with 3D V-Cache in 2027), while 'Verano' with LPDDR memory arrives in H2 2027.
- EPYC 9006 SP7 availability is Q4 2026, and AMD commits to fair benchmarking without restrictions on Phoronix.
- AMD claims Venice delivers decisive wins over Intel Xeon and ARM competitors, with Intel's Xeon Diamond Rapids not expected until at least 2027.