Show HN: Write, simulate and synthesize VHDL/Verilog in the browser

6 days ago

Learn VHDL and SystemVerilog by writing real code with instant syntax feedback.
Run simulations using GHDL and Icarus, and synthesize designs with Yosys in seconds.
Explore interactive waveforms and block diagrams that link back to the code.
Access a structured curriculum with 106 lessons, 115 live examples, 111 exercises, and 50 challenges.
No setup required: everything runs in the browser, ready in seconds.
Practice with story-driven HDL challenges that have real testbenches.
Multi-language support: write VHDL or SystemVerilog on the same EDA toolchain.
Free Fundamentals level with lessons, exercises, and instant feedback.
Use the Playground to simulate, synthesize, and explore your own designs without an account.

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