Device Clock Generation
5 hours ago
- #FPGA ASIC integration
- #digital design
- #clock generation
- Discusses generating a device clock for external peripherals in digital logic for both FPGA and ASIC designs.
- Highlights challenges in device clock generation: dynamic frequency changes, pausing, DDR signaling with 90-degree offset, and ensuring glitch-free operation.
- Proposes a solution using a 'wide clock' (multi-bit) output via OSERDES/ODDR, keeping all logic in the source clock domain to avoid clock domain crossings.
- Describes a clock generator module with configurable frequency, phase offset, and shutdown capability, and includes formal verification and simulation methods.
- Outcomes include a flexible, reliable clock generator suitable for various protocols (e.g., SDIO/eMMC, HyperRAM) that works in both FPGA and ASIC environments.