CPPL: A Circuit Prompt Programming Language
a day ago
- #hardware design
- #LLM automation
- #compiler framework
- CPPL is a compiler-mediated design framework for LLM-assisted hardware generation.
- It combines a Python frontend DSL for module interfaces with CPPL IR, a JSON-based circuit IR.
- The compiler infers operation widths, validates IR, checks hierarchy and port bindings.
- CPPL lowers the result to CIRCT for synthesizable Verilog generation.
- It improves functional correctness over direct Verilog or CIRCT IR generation on the RTLLM benchmark.
- CIRCT optimization reduces post-synthesis AIG node counts.
- The framework makes LLM-assisted hardware design more reliable, analyzable, and amenable to backend optimization.