RISC-V and Floating Point
2 days ago
- #Floating-Point
- #RISC-V
- #ISA Extensions
- RISC-V base ISA (RV32I/RV64I) lacks native floating-point instructions, requiring extensions for floating-point arithmetic support.
- F extension introduces single-precision floating-point (binary32) with a dedicated Floating-Point Register File (FRF), aligned with IEEE-754-2008 standard, including FMA operations.
- Additional scalar extensions include D (double-precision binary64), Q (quad-precision binary128, limited adoption), and Zfh/Zfhmin (half-precision binary16).
- Zfa extension adds useful scalar operations like floating-point load immediate and quiet comparisons for standard formats.
- Zfinx family allows floating-point operations using the general-purpose register file (XRF) instead of FRF, reducing hardware cost.
- Vector floating-point support via RVV 1.0 includes single/double precision, widening/narrowing operations, and destructive FMA variants, with extensions like Zvfh/min for half-precision and Zvfbfmin/wma for BFloat16.
- Non-standard formats supported: BFloat16 (via Zfbfmin, Zvfbfmin/wma) and OpenCompute OFP8/OFP4 (via Zvfofp8min and proposed Zvfofp4min).
- Future developments may include support for micro-scaling (e.g., MX scaling formats) and IEEE P3109 small precision formats for machine learning.
- Challenges include balancing rapid market needs with long-term standardization and managing competing floating-point format standards.
- RISC-V floating-point extensions range from minimal Zfinx for low-end to comprehensive vector support, with ongoing work in dot products, matrix operations, and cryptographic primitives.