DDR4 Sdram – Initialization, Training and Calibration
4 days ago
- #DDR4
- #Memory Training
- #Hardware Initialization
- DDR4 SDRAM initialization involves 4 phases: Power-up and Initialization, ZQ Calibration, Vref DQ Calibration, and Read/Write Training.
- Power-up and Initialization sequence includes applying power, de-asserting RESET, enabling clocks, issuing MRS commands, and performing ZQ Calibration.
- ZQ Calibration tunes the internal 240Ω resistors in DQ pins to match an external precision resistor, ensuring signal integrity.
- Vref DQ Calibration in DDR4 uses an internal voltage reference (VrefDQ) instead of a voltage divider, set via mode registers.
- Read/Write Training aligns clock and data strobe signals, determines correct read/write delays, and centers the data eye for reliable operation.
- Write Leveling compensates for skew between Clock and DataStrobe to maintain tDQSS timing at each DRAM on the DIMM.
- MPR Pattern Write is a preparatory step for Read and Write Centering, using Multi-Purpose Registers for training.
- Read Centering trains the controller to capture data at the center of the data eye by adjusting internal read delays.
- Write Centering ensures write data is centered on the corresponding write strobe edge at the DRAM by adjusting write delays.
- Periodic Calibration (ZQCS and Periodic Read Centering) may be required to maintain signal integrity under varying voltage and temperature conditions.