Examining circuit boards from the Space Shuttle's I/O Processor

4 days ago

The Space Shuttle’s five general-purpose computers, each consisting of a CPU and an I/O Processor (IOP), controlled engines, monitored sensors, displayed data, and navigated the Shuttle.
The IOP was a separate programmable computer with an unusual multi-threaded architecture, running 25 virtual processors with two different instruction sets (BCE and MSC) to manage network ports and ensure predictable performance.
The IOP included network interface pages (MIA) that handled analog-to-digital conversion, Manchester encoding, and communication over 24 high-speed data bus networks for reliability and redundancy.
A PROM page stored microcode in fusible-link PROM chips, which defined the low-level instructions for the IOP’s virtual processors, enabling them to run on a single physical processor.
The computer system used advanced packaging with ‘pages’—dual-sided circuit boards with flat-pack ICs—and was later upgraded to the AP-101S, combining the CPU and IOP into one unit to save weight and improve performance.
Key technologies included Manchester encoding for data transmission, hybrid modules for analog circuitry, and a barrel processor design inspired by the CDC 6600 supercomputer.

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