486Tang – 486 on a credit-card-sized FPGA board
8 hours ago
- #x86
- #RetroComputing
- #FPGA
- 486Tang v0.1 is a port of the ao486 MiSTer PC core to the Sipeed Tang Console 138K FPGA, marking the first time ao486 has been ported to a non-Altera FPGA.
- Key differences from the MiSTer core include switching to SDRAM for main memory, implementing SD-backed IDE, and adding a boot-loading module for BIOS and other boot essentials.
- Verilator was used for subsystem and whole-system simulation to debug and bring up the system efficiently, with specific instrumentation hooks for BIOS debug strings and subsystem tracing.
- Performance optimizations addressed long combinational paths, including reset tree and fan-out reduction, instruction fetch optimization, and TLB optimization, improving performance to roughly 486SX-20 levels.
- The project highlights the complexity of x86 architecture compared to ARM, with reflections on clock speed scaling and the trade-offs between compatibility and simplicity in CPU design.