Symmetric MultiProcessing, Hyper-Threading and Scheduling on Maestro
8 hours ago
- #Scheduling
- #SMP
- #ACPI
- SMP (Symmetric MultiProcessing) support has been implemented in Maestro to utilize multiple CPU cores for faster compilation.
- ACPI (Advanced Configuration and Power Interface) is used for enumerating CPU cores, despite its complexity and criticism for being Windows-centric.
- The APIC (Advanced Programmable Interrupt Controller) replaces the legacy PIC (Programmable Interrupt Controller) and PIT (Programmable Interval Timer) for handling interrupts in multi-core systems.
- APIC timer calibration is necessary for accurate timing, achieved by comparing it with the HPET (High Precision Event Timer).
- Starting additional CPU cores involves sending INIT and STARTUP IPIs (Inter-Processor Interrupts) with precise delays.
- Halting all CPU cores requires a global flag and IPIs to ensure all cores stop execution uniformly.
- Per-CPU structures store core-specific information, including scheduler run queues, enabling independent scheduling per core.
- TLB (Translation Lookaside Buffer) shootdowns ensure memory mapping consistency across cores by invalidating cached translations.
- Deferred calls allow functions to be executed on specific CPU cores, facilitating inter-core communication.
- The scheduler has been rewritten to support per-core run queues and process load balancing inspired by FreeBSD's ULE scheduler.
- Critical sections disable preemption while allowing interrupts, improving concurrency control.
- Hyper-Threading divides physical cores into logical cores, sharing caches and requiring careful scheduling to optimize performance.
- A CPU topology tree is built at boot to represent core relationships, aiding in efficient process scheduling.
- Current limitations include lack of PIT support, no x2APIC implementation, and memory contention issues.
- Future improvements may include RCU (Read-Copy-Update) mechanisms and better interrupt handling.