Z8086: Rebuilding the 8086 from Original Microcode
9 hours ago
- #x86
- #microcode
- #FPGA
- z8086 is a project to rebuild the 8086/8088 core using original Intel microcode.
- The core loads a recovered 512x21 ROM to recreate the micro-architecture, avoiding hand-coding instructions.
- z8086 is FPGA-friendly, running on a single clock domain and using around 2500 LUTs with a 60 MHz clock speed.
- The 8086 is studied for its foundational x86 features like segmented addressing and ModR/M.
- Reverse-engineering resources like Ken Shirriff's blog and Andrew Jenner's microcode disassembly enabled faithful replication.
- Key goals include accuracy, educational value, and practicality for FPGA projects.
- The 8086's pipeline includes a prefetch queue, loader, microcode sequencer, and EU/BIU datapath.
- Microcode efficiently handles a wide CISC ISA with minimal transistors compared to other CPUs like the 6502 and 68000.
- Discrepancies found in the original 8086 patent's FC/SC formulas were corrected during implementation.
- The 8086's interrupt bug, affecting MOV SS and POP SS instructions, is faithfully reproduced in z8086.
- The prefetch queue's 8-bit bus design limits performance, a bottleneck later addressed in CPUs like the 386.
- Future plans include more FPGA testing, booting DOS, and potential WebAssembly compilation for browser visualization.