Parallelizing SHA256 Calculation on FPGA
10 months ago
- #Cryptography
- #SHA-256
- #FPGA
- Implementation of a parallel SHA-256 hash calculator on FPGA to improve performance.
- Optimization of the SHA-256 core by sharing the K matrix among all cores and parallelizing W matrix initialization.
- Introduction of the sha256_core_pif module with a parallel interface for reduced logic usage and higher performance.
- Development of a SHA256_manager module to coordinate multiple hash cores for simultaneous hash computations.
- Application of the system as a password cracker, iteratively hashing candidate strings to match a target hash.
- Integration of 12 sha256_core_pif modules on a Litefury board connected to a Raspberry Pi 5 via PCIe, with timing adjustments.
- Creation of a Python driver for host-side management, utilizing xDMA drivers and AXI peripheral communication.
- Demonstration of the system's capability to recover original strings from their SHA-256 hashes.
- Highlighting the potential of FPGAs in cryptography and cybersecurity for parallel processing and acceleration.