Hasty Briefsbeta

Designing a Low Latency 10G Ethernet Core

7 hours ago
https://ttchisholm.github.io/ethernet/2023/05/01/designing-10g-eth-1.html
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  • #Ethernet
  • #Low Latency
  • #FPGA
  • First in a series about developing a low latency 10G Ethernet core for FPGA.
  • Personal project aimed at gaining expertise in low latency FPGA design and high-speed Ethernet.
  • Design achieves less than 60ns loopback latency, comparable to commercial offerings.
  • Focus on unique aspects like verification tools (cocotb, pyuvm), latency reduction techniques, and commercial core analysis.
  • Includes resources for those unfamiliar with Layer 1/2 Ethernet.
  • Next post will cover design overview and verification.
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