Floating Point Fun on Cortex-M Processors
2 days ago
- #Embedded Systems
- #Compiler Flags
- #Arm Floating Point
- The article explains Arm's floating point ABIs: soft, softfp, and hard, and the resulting linker errors when mixing them.
- Soft ABI emulates floating-point operations in software, softfp uses FPU instructions but passes arguments in integer registers, and hard uses FPU instructions and registers.
- The nRF52840 and ESP32-S3 examples illustrate how different ABIs affect code generation, with specific assembly outputs shown.
- Zephyr's configuration options (CONFIG_FPU, CONFIG_FP_HARDABI, CONFIG_FP_SOFTABI) control the FPU and ABI selection.
- Enabling the FPU dynamically is possible but risky; an example demonstrates handling No Coprocessor (NOCP) faults.
- Floating point operations without FPU enabled cause exceptions, but can be managed via runtime enabling or fault handlers.
- The article hints at future discussions on trade-offs between hardware and software floating point implementations.