NVC: VHDL Compiler and Simulator
a year ago
- #VHDL
- #Compiler
- #Simulation
- NVC is a VHDL compiler and simulator supporting VHDL-2008 and experimental VHDL-2019.
- It focuses on simulation performance using LLVM to compile VHDL to native machine code.
- NVC is not a synthesizer; it only implements simulation behavior per IEEE 1076 standard.
- Supports verification frameworks like OSVVM, UVVM, VUnit, and cocotb.
- Simulation involves three steps: analyzing, elaborating, and running the design.
- NVC is free software under GNU GPL v3+, with some libraries under Apache 2.0.
- Available on multiple platforms including Linux, macOS, and Windows via MSYS2.
- Installation options include package managers (brew, winget) and building from source.
- Supports various VHDL standards (1993, 2000, 2002, 2008, 2019) with --std argument.
- Includes scripts to compile popular verification frameworks and FPGA vendor libraries.