Samsung Demonstrates 3D Stacked FETs with Triple Nanosheet Channels at 42nm
a day ago
- #nanosheet channels
- #3D Stacked FET
- #semiconductor scaling
- Samsung presented a 3D Stacked FET paper at the 2026 VLSI Symposium, achieving a gate pitch of 42 nm with triple-stacked nanosheet channels.
- The research addresses scaling challenges by vertically stacking n-type and p-type transistors to increase density, overcoming limitations of planar layouts.
- Key innovations include triple-stacked nanosheet channels for current drive, advanced epitaxial growth for uniform crystal layers, and Middle Dielectric Isolation (MDI) for electrical separation.
- Demonstrating a 42 nm gate pitch shows 3D Stacked FETs are evolving into a practical technology for next-generation logic devices, building on Gate-All-Around (GAA) foundations.