Machine Scheduler in LLVM – Part I
15 hours ago
- #Machine Scheduler
- #LLVM
- #Instruction Scheduling
- LLVM's scheduling model encodes low-level details and has potential for broader use.
- Instruction scheduler in LLVM is a primary user of scheduling models, with Machine Scheduler being the focus.
- Machine Scheduler operates on Machine IR, aiming to reduce register pressure and improve instruction-level parallelism.
- ScheduleDAGInstrs represents a MachineBasicBlock, with each MachineInstr modeled by SUnit, detailing dependencies and latencies.
- Machine Scheduler's workflow involves picking nodes from a queue, simulating their timeline, and updating states.
- Scheduling timeline and boundary (SchedBoundary) manage cycle tracking and instruction issuance, supporting top-down and bottom-up scheduling.
- Candidate instructions are divided into pending and available queues, with profitability checks determining the best candidate.
- Hazard detection includes data hazard (operand readiness) and structural hazard (resource availability), crucial for in-order cores.
- Data hazard detection uses ready cycles to ensure instructions wait for operands, while structural hazard uses ReservedCycles for resource availability.
- Soft stalls in latency devices (unbuffered resources) are considered in profitability checks, balancing between in-order and out-of-order execution.