Fleet: Hierarchical Task-Based Abstraction for Megakernels on Multi-Die GPUs
3 hours ago
- #GPU Programming
- #Chiplet Architecture
- #Megakernel Optimization
- Fleet is a multi-level task model for multi-die GPUs, introducing Chiplet-tasks to bind work and data to a chiplet for better locality and synchronization.
- It addresses the mismatch between flat GPU programming models (CUDA/HIP) and chiplet-based designs, reducing redundant memory traffic and improving cache utilization.
- On AMD Instinct MI350 with Qwen3-8B, Fleet lowers decode latency by 1.3-1.5x at small batch sizes and achieves up to 1.30x speedup at larger batches via cooperative weight tiling and increased L2 hit rates.