Examining circuit boards from the Space Shuttle's I/O Processor
12 hours ago
- The Shuttle's computers used a split architecture with a main CPU and a complex I/O Processor (IOP) featuring an unusual multi-threaded design with 25 virtual processors and two instruction sets.
- The IOP's network interface pages (MIA) converted data to Manchester encoding, using custom hybrid modules, transformers, and shift registers to handle 24 high-speed data bus networks.
- Each IOP page consisted of two circuit boards sandwiching a metal plate for conduction cooling, with the interface pages densely packed with flat-pack ICs and the microcode PROM page using larger DIP chips.
- The IOP's architecture, developed by Peter Kogge, used a barrel processor design where virtual processors (BCE and MSC) took turns executing micro-instructions stored in fusible-link PROM chips.
- Manchester encoding was chosen for the Shuttle's networks to eliminate DC component and provide reliable bit separation, a technique still used in modern systems like Ethernet.