Condor's Cuzco RISC-V Core at Hot Chips 2025
11 days ago
- #CPU-Design
- #RISC-V
- #High-Performance
- Condor Computing, a subsidiary of Andes Technology, specializes in licensable RISC-V cores, similar to Arm and SiFive.
- Condor's Cuzco core, presented at Hot Chips 2025, is a high-performance RISC-V design with wide out-of-order execution and a modern branch predictor.
- Cuzco uses a 'time-based' scheduling scheme in the backend to save power and reduce complexity, without requiring ISA modifications.
- The core is 8-wide out-of-order with a 256 entry ROB, targeting clock speeds of 2 GHz to 2.5 GHz on TSMC’s 5nm process.
- Cuzco features a sophisticated branch predictor (TAGE-SC-L), a 64 KB instruction cache, and a 64 entry TLB for fast address translation.
- The rename and allocate stage in Cuzco predicts instruction schedules using a Time Resource Matrix (TRM), reducing the need for dynamic scheduling.
- Cuzco's execution resources are grouped into slices, each capable of handling all RISC-V instructions, with configurable queue sizes.
- The load/store unit includes a 64 entry load queue, a 64 entry store queue, and supports up to 64B/cycle load bandwidth.
- Cuzco supports 256/512-bit VLENs for vector operations, with one FMA unit per slice and configurable L2/L3 cache sizes.
- Condor's approach with Cuzco aims to innovate within the out-of-order execution model while maintaining compatibility and performance.