Is x86 ready to ACE it?
4 hours ago
- #Instruction Set Extensions
- #Machine Learning Acceleration
- #CPU Architecture
- CPU designs evolve with instruction set extensions to match changing workloads, such as Intel's AMX for machine learning.
- AMX accelerates matrix multiplication using tile registers and TMUL accelerator, supporting INT8, FP16, and BF16 data types.
- ACE (AMX accelerator) introduces outer product instructions, supports FP8, and uses AVX-512 vector registers for inputs.
- Compared to Arm's SME/SME2, ACE leverages fixed 512-bit vector widths for data conversion, while SME uses variable vector lengths.
- ACE includes a Block Scale Register (BSR0) for scaling in low-precision formats like FP8, similar to Arm's SME scaling support.
- Tile size optimization reduces memory bandwidth; ACE's use of AVX-512 registers allows larger tiles than AMX, improving efficiency.
- ACE's tile registers can theoretically be used as a scratchpad, but practical limitations like capacity and latency make it less feasible.
- Hardware implementation will be key to ACE's performance, with no current hardware available, but potential future support from Intel and AMD.