OpenSTA: Open-source static timing analysis for FPGAs
19 hours ago
- #OpenSTA
- #Timing Analysis
- #FPGA
- The Logik FPGA toolchain now includes OpenSTA for post-implementation static timing analysis.
- OpenSTA integration allows for a separate, user-driven timing analysis step with a comprehensive UI.
- OpenSTA provides superior SDC command support compared to other open-source and commercial tools.
- The new flow offers interactive TCL interface for granular control over timing analysis.
- A demo script showcases how to use the upgraded flow with breakpoints for interactive timing analysis.