- The project rebuilds the MOS 6502 CPU using 4,051 individual discrete transistors (SOT-323 packages) on a large A4-sized board, replicating the original silicon die layout transistor-for-transistor.
- It uses the original dynamic NMOS logic design, not static logic, relying on charge stored on wire capacitance and requiring clock refresh, with 1,023 pull-up resistors replacing depletion-mode loads.
- The board operates at 10–20 kHz (vs. 1 MHz original) to allow visual observation of operation; it includes 55 register LEDs to show CPU state.
- Verification is done entirely through simulation and netlist equivalence before fabrication, with no physical board yet built; the first power-up is the real test.
- A Raspberry Pi Pico 2 W provides clock and memory emulation, making the board self-contained for testing.