Speedrunning a CPU: RISC-V in a Week
7 days ago
- #Performance
- #Emulator
- #RISC-V
- The author embarked on a challenge to create a RISC-V emulator from scratch in one week, aiming for high performance.
- Initially considered making an assembler but abandoned the idea due to complexity and lack of immediate utility.
- Struggled with the extensive RISC-V documentation (727 pages) but found a more concise reference guide.
- Implemented a basic RISC-V emulator, starting with simple instructions and gradually adding more complex ones.
- Faced challenges in verifying the correctness of the emulator and initially ignored the RISC-V Test Suite.
- Optimized performance by implementing an Instruction Cache to reduce decoding overhead.
- Improved emulator speed from 160 MIPS to 550 MIPS through optimizations, though details were not fully explained.
- Explored additional features like timers and CSRs but ran out of time to document them thoroughly.