Instruction decoding in the Intel 8087 floating-point chip
10 days ago
- #microcode
- #8087
- #floating-point
- The 8087 coprocessor decodes instructions using a combination of logic gates, PLAs, and microcode.
- It watches the 8086's bus to identify ESCAPE opcodes meant for floating-point operations.
- The 8087 offloads memory address computation to the 8086 by observing bus activity.
- Instructions are structured with a ModR/M byte, complicating decoding but enabling efficient operation.
- Microcode routines handle most instructions, with shared routines for similar operations like addition and subtraction.
- PLAs (Programmable Logic Arrays) optimize instruction decoding by matching bit patterns efficiently.
- Hardwired circuits in the Bus Interface Unit (BIU) handle specific instructions like interrupt control and state save/restore.
- Constants like π are stored in a ROM, with microcode adjusting exponents on the fly to save space.
- The 8087's design prioritizes transistor efficiency, leading to a complex but compact architecture.
- Early manufacturing yields were low, with only two working chips per wafer, but the 8087's architecture became foundational for floating-point standards.