Re-architecting End-host Networking with CXL
4 days ago
- #CXL
- #Hardware
- #Networking
- The paper discusses re-architecting end-host networking using CXL to address coherence, memory, and offloading challenges.
- CXL Type-1 devices allow NICs coherent access to host memory, enabling efficient prefetching of receive descriptors and reducing host memory reads.
- CXL Type-2 NICs can store packets and descriptors in NIC memory, with host CPU caching and intelligent use of NC-P operations for direct LLC writes.
- The authors implemented a CXL NIC on an Altera FPGA, showing improved loopback latency compared to an nVidia BlueField-3 PCIe NIC.
- CXL coherence messages are highlighted as more efficient than MMIOs and interrupts, though polling memory locations is noted as potentially wasteful.