Disrupting the DRAM roadmap with capacitor-less IGZO-DRAM technology
21 hours ago
- #IGZO
- #DRAM
- #Memory Technology
- Traditional DRAM memory cells consist of one capacitor (1C) and one silicon-based transistor (1T).
- Scaling issues since 2015 have led to a 'memory wall' due to capacitor constraints and leakage paths.
- In 2020, imec introduced a novel 2T0C DRAM bit cell using IGZO-based transistors, eliminating the capacitor.
- IGZO transistors offer extremely low off current, improving retention time, refresh rate, and power consumption.
- The 2T0C design simplifies fabrication, is cost-effective, and enables BEOL processing and 3D stacking.
- Experimental demonstrations showed retention times >400s, 1000x longer than traditional DRAM.
- Further optimizations in 2021 improved retention to >1000s and endurance to >10^11 cycles.
- Recent advancements include RIE patterning, achieving retention >4.5 hours and enabling 3D integration.
- Research groups worldwide are exploring alternative configurations and materials like IWO and ITO.
- IGZO-DRAM is now on the long-term roadmap, with potential for high-density embedded DRAM (eDRAM).
- Reliability concerns, particularly PBTI in IGZO transistors, are being addressed for industry adoption.