Porting Gigabyte MZ33-AR1 Server Board with AMD Turin CPU to Coreboot
8 days ago
- #coreboot
- #AMD-Turin
- #firmware-development
- The blog post details the first phase of enabling AMD Turin support in coreboot and porting the Gigabyte MZ33-AR1 board, funded by NLnet Foundation.
- AMD's open-source firmware initiative for Turin CPUs inspired the project, with OpenSIL aiming to unify silicon initialization across firmware frameworks like EDK2 and coreboot.
- Milestones included integrating Turin PSP firmware, creating a Turin SoC skeleton in coreboot, and setting up a mainboard skeleton for MZ33-AR1.
- The Turin SoC skeleton was based on Genoa's, with adjustments for Turin's architecture, including changes to USB ports, AOAC registers, and PCI domain layouts.
- PSP firmware preparation involved CPU-specific and board-specific blobs, with challenges in stitching blobs for Turin not present in Genoa.
- APCB blobs, crucial for memory configuration, were extracted from the vendor image using PSPTool, with improvements made to the tool for better parsing.
- The mainboard setup focused on minimal bootblock execution, with serial console support and initial board-specific code for early boot stages.
- Building coreboot images required workarounds due to PSP blob stitching issues, with successful bootblock execution confirmed via serial output.
- Future project phases aim to enhance Turin OpenSIL support, with all current patches available under the 'turin_poc' topic on coreboot's Gerrit.
- The post acknowledges contributors and tools like PSPTool and UEFITool, and outlines a roadmap for secure, vertically integrated applications using Dasharo Pro Package.