Hasty Briefsbeta

Open-Source Hardware: curated list of open-source ASIC tools and designs

a day ago
  • #open-source-hardware
  • #EDA-tools
  • #RISC-V
  • A curated list of awesome open source hardware tools, generators, and reusable designs.
  • Categorized and alphabetical (per category) list of open source hardware projects.
  • Requirements include linking to source code repositories, open source projects only, and working projects (not WIP/rusty).
  • Includes benchmarks, board design, digital design, FPGA design, formal verification, linters, register design, schematics, simulators, verification frameworks, physics, and waveform viewers.
  • Accelerators, AIB, AXI, analog circuits, chip packaging, boards, connectivity, CPUs, FPGA architectures, libraries, memory, and systems are covered.
  • PDKs like asap7, freepdk45, and probe3.0 are included.
  • Tools for analog circuit design, hardware agents, SPICE netlist datasets, and HDL build systems.
  • Dependency management tools, SoC design frameworks, EDA tool interfacing libraries, and build system generators.
  • Logic synthesis, formal verification, hardware design frameworks, and intermediate languages for hardware accelerators.
  • Hardware description languages (HDLs) like Chisel, Bluespec, and SystemVerilog.
  • Circuit IR compilers, graph-based circuit tools, and dataflow compilers for QNN inference.
  • Optimization tools for DNN models, symbolic reasoning for Boolean networks, and VHDL synthesis.
  • Hardware generators, parsers, and interactive synthesis tools.
  • High-level hardware specification platforms, Python-based hardware design languages, and logic network libraries.
  • Structural netlist APIs, high-level synthesis frameworks, and hardware description languages with automatic pipelining.
  • Python-based hardware generation, simulation, and verification frameworks.
  • SystemVerilog parsers, optimizers, and converters.
  • Formal verification tools, SMT solvers, and model checkers.
  • SystemVerilog linters, style checkers, and simulators.
  • Register generation tools, schematic visualizers, and EDA tools.
  • Circuit simulators, FPGA-accelerated hardware simulators, and modular simulator platforms.
  • VHDL and Verilog simulators, DRAM simulators, and CPU emulators.
  • Verification frameworks, UVM testbenches, and Python-based cosimulation libraries.
  • Waveform viewers, oscilloscope applications, and signal analysis tools.
  • Hardware accelerators for AES, vector units, matrix multiplication, and deep learning.
  • FPGA-based accelerators, GPUs, and custom instruction-set processors.
  • AXI and APB verification IP, bus bridges, and interface modules.
  • Analog design tools, mixed-signal SoC synthesis frameworks, and open-source PMICs.
  • Hardware packaging, motherboards, and open-source board designs.
  • DDR controllers, HDMI implementations, I2C masters, and Ethernet cores.
  • NoC routers, PCIe cores, and USB implementations.
  • RISC-V CPUs, POWER processor cores, and customizable MCU-class processors.
  • FPGA generators, fabric CAD tools, and prototyping frameworks.
  • SystemVerilog component libraries, floating-point units, and hardware abstraction libraries.
  • Cache designs, SRAM compilers, and memory generators.
  • SoC architectures, heterogeneous platforms, and open-source silicon roots of trust.
  • FPGA development boards, testbeds, and evaluation boards.
  • Educational resources, computer architecture courses, and open hardware materials.
  • Hardware verification resources, EDA tools, and semiconductor startups.