Vectorization of Verilog Designs and its Effects on Verification and Synthesis
3 days ago
- #Verilog
- #Vectorization
- #Formal Verification
- Vectorization is a compiler optimization that replaces scalar operations with vector operations.
- Verilog lacks common vectorization despite supporting vector notation, due to no semantic guarantees.
- Vectorization reduces symbolic complexity, benefiting formal verification tools like Cadence Jasper.
- A Verilog vectorizer built on CIRCT recognizes patterns like inverted assignments and complex expressions.
- The vectorizer improves Jasper's elaboration time by 28.12% and reduces memory usage by 51.30% on 1,157 designs.