Panther Lake's Reveal at ITT 2025 – By George Cozma
a day ago
- #Xe3-GPU
- #Intel
- #Panther-Lake
- Intel announced Panther Lake (PTL) SoC at ITT, featuring a new node, CPU core improvements, and a new GPU.
- Panther Lake has 3 tiles: Compute (CPU, NPU, Media engines), GPU (Xe3), and Platform Controller (I/O).
- Smallest configuration: 4 P-Cores, 4 LP E-Cores, 8MB cache (18A node), 4 Xe3 GPU cores (Intel 3 node).
- Middle configuration: 4 P-Cores, 8 E-Cores, 4 LP E-Cores, 18MB L3 + 8MB cache, 20 PCIe lanes.
- Largest configuration: Same CPU as middle, 12 Xe3 GPU cores (TSMC N3E), largest iGPU for client SoC.
- Xe3 GPU: 6 Xe Cores per render slice (vs. 4 in Xe2), 16MB L2, 50% performance uplift over Lunar Lake.
- CPU cores: Cougar Cove (P-Core) and Darkmont (E-Core) focus on BPU improvements and memory disambiguation.
- Intel claims 10% single-thread, 40% perf/W over Arrow Lake; 50% multi-thread over Lunar Lake.
- NPU and Media Engine: FP8 support, 40% smaller NPU, AVC 10b decode/encode.
- Launch at CES 2026, review samples by January 2026.