The Evolution of x86 SIMD: From SSE to AVX-512
7 days ago
- #x86
- #CPU-architecture
- #SIMD
- The evolution of x86 SIMD from MMX to AVX-512 is a story of technological innovation, corporate competition, and engineering compromises.
- MMX, introduced by Intel in 1997, was a significant gamble, developed by Intel's Israel team, marking the first flagship processor designed outside the U.S.
- A controversial decision in MMX design was register aliasing, which mapped MMX registers onto existing x87 floating-point registers to avoid OS modifications, but limited mixed floating-point and MMX instruction usage.
- Intel's aggressive marketing of MMX, including a Super Bowl ad, led to high expectations, but real-world performance gains were modest without optimized software.
- AMD's 3DNow! forced Intel to accelerate its development of SSE, which introduced 128-bit registers and floating-point SIMD capabilities.
- SSE2 expanded SIMD to double-precision floating-point operations, driven by the need to compete with AMD's Athlon processors in gaming and 3D graphics.
- AVX introduced 256-bit registers and non-destructive three-operand instructions, improving compiler efficiency and reducing register spilling.
- The FMA controversy between Intel and AMD highlighted the challenges of instruction set fragmentation, with Intel's FMA3 eventually becoming the standard.
- AVX-512, initially developed for Xeon Phi and high-performance computing, faced criticism for power consumption, thermal issues, and fragmentation across different CPU generations.
- Linus Torvalds famously criticized AVX-512 as a 'power virus,' leading to its eventual disablement in Intel's hybrid architecture CPUs like Alder Lake.
- AMD's approach to AVX-512 in Zen 4, using double-pumping on 256-bit units, avoided the power penalties of Intel's implementation, showcasing a more efficient design.
- The legacy of x86 SIMD is a mix of brilliant engineering, marketing hype, and lessons on the importance of backward compatibility, competition, and market-driven decisions.