Deep Dive into SATA, USB and PCI Express on AMD Turin
7 hours ago
- #firmware
- #computer-hardware
- #io-buses
- The term 'computer' originates from 'computing', highlighting the processor's processing capabilities.
- Computers require operating systems or software to utilize their computing power, stored typically on disks.
- Communication buses like SATA, USB, and PCI Express facilitate data exchange between processors and peripherals, known as I/O buses.
- Firmware initializes modern computers, preparing them to run software by initializing CPUs and I/O buses.
- The blog focuses on initializing I/O buses on AMD Turin processor-based systems and the Gigabyte MZ33-AR1.
- SATA and USB are crucial for human-usable PCs, with SATA being superseded by NVMe but still used in NAS/RAID setups.
- USB's versatility allows connection of various devices, from storage to input devices.
- The Gigabyte MZ33-AR1 features up to 16 SATA ports and multiple USB ports, requiring port mapping for proper configuration.
- Port mapping involves plugging drives into each port and using Linux utilities like `lsusb` and `dmesg` to identify connections.
- USB port mapping revealed connections through Realtek hubs, contrary to the board manual's block diagram.
- SATA ports on the MZ33-AR1 are accessed via MCIO connectors, requiring specific cables for connection and power.
- SATA controllers were mapped to SCSI hosts, with specific PCI domains identified for each controller.
- Turin CPU architecture divides PCI topology into 8 domains, each with a root bridge, crucial for understanding device initialization.
- SERDES (Serializer/Deserializer) in Turin CPUs organizes physical lanes for PCIe, CXL, and SATA, with specific groupings and bifurcation options.
- Understanding SERDES organization is key to configuring high-speed lanes for SATA and other buses.
- Physical lane numbers and GPP bridges are essential for initializing SATA ports correctly in coreboot.
- Despite progress in mapping and configuration, testing SATA and USB functionality is pending due to early CPU initialization issues.
- Milestones achieved include hardware topology discovery for USB and SATA and partial completion of port configuration in coreboot.