gpu architecture

The Anatomy of an Instruction Pipeline Hazard

2 months ago

The article discusses the necessity of hardware-based validation for instruction schedules in deep-pipeline GPUs like the NVIDIA B200, as static analysis alone is insufficient and can lead to silent correctness bugs due to under-stalling.
It highlights specific pipeline hazards, including predicate-consumer under-stalls where a branch reads a stale predicate value, and fixed-latency RAW under-stalls in operations like FFMA and DFMA, emphasizing the need for precise latency measurements through on-silicon probing.
The article explains variable-latency operations (e.g., LDG, LDS) that rely on scoreboard mechanisms for dependency tracking, and proposes crash-amplified load-use hazards as a method for deterministic failure detection in CI systems.
It stresses that compiler engineers must rely on silicon as the ultimate arbiter of correctness, advocating for systematic hardware hazard registries and reproducible on-silicon tests to validate scheduling logic against pipeline realities.