Video2NAND – Abusing video codecs for great computational power

2 days ago

The article explores building logic circuits using VP8 video codec prediction mechanisms instead of transistors.
Video codecs encode video frames, with key-frames being independent and inter-frames referencing previous ones.
In this setup, white blocks represent True (255) and black blocks represent False (0).
Wires are modeled using H_PRED (horizontal prediction) and V_PRED (vertical prediction) modes.
The TM_PRED mode is used to construct NOT and AND gates, forming a functionally complete set.
A NOT gate is implemented as 255 - input by setting top row to 255 and left column to 0.
An AND gate is made by setting top_left to 255 and using top row and left column as inputs.
These gadgets can be combined to create more complex gates like NAND.
Open questions include optimizing gadgets, integrating with synthesis tools, and exploring sequential logic with inter-frames.

The article describes implementing a digital circuit simulator in Haskell, closely following SICP's approach using mutable state and message-passing.
Wires are defined with IORefs for signal value and action procedures, enabling the observer pattern where downstream components subscribe to signal changes.
Basic gates (inverter, and_gate, or_gate) are implemented as action procedures that update output wires after a delay, using a global mutable agenda for scheduling.

The author built a physical 17x17 matrix of switches with integrated LEDs to simulate Conway's Game of Life, using a microcontroller (AVR128DA64) to control rows and columns.
The LED display uses a multiplexing scheme where each row is active for 1/17th of the time, requiring higher current (150 mA per LED) to maintain brightness, with MOSFETs for row and column switching.
User input is detected by reusing row select lines to ground and sensing switch closures via GPIO pins, with pull-up resistors integrated on the MCU.

<antirez>8 days ago

Vector Sets are a new Redis data type for vector similarity, similar to Sorted Sets but with vectors as scores.
They are implemented in the Redis core using the modules API, blending modularity and native support starting from Redis 8.
The underlying HNSW graph is rewritten from scratch with true deletions (no tombstones) and enforced reciprocal links to maintain connectivity.

The MMI 5300 is a 1024-bit PROM from the early 1970s, programmed once by blowing fuses.
Data is stored in a 33×33 array of diodes and fuses; intact fuses represent 1, blown fuses represent 0.
Address decoding splits into column selection (A3-A7) and output selection (A0-A2) to access 256 4-bit words.

The article describes implementing a digital circuit simulator in Haskell, closely following SICP's approach using mutable state and message-passing.
Wires are defined with IORefs for signal value and action procedures, enabling the observer pattern where downstream components subscribe to signal changes.
Basic gates (inverter, and_gate, or_gate) are implemented as action procedures that update output wires after a delay, using a global mutable agenda for scheduling.

The author built a physical 17x17 matrix of switches with integrated LEDs to simulate Conway's Game of Life, using a microcontroller (AVR128DA64) to control rows and columns.
The LED display uses a multiplexing scheme where each row is active for 1/17th of the time, requiring higher current (150 mA per LED) to maintain brightness, with MOSFETs for row and column switching.
User input is detected by reusing row select lines to ground and sensing switch closures via GPIO pins, with pull-up resistors integrated on the MCU.

<antirez>8 days ago

Vector Sets are a new Redis data type for vector similarity, similar to Sorted Sets but with vectors as scores.
They are implemented in the Redis core using the modules API, blending modularity and native support starting from Redis 8.
The underlying HNSW graph is rewritten from scratch with true deletions (no tombstones) and enforced reciprocal links to maintain connectivity.

The MMI 5300 is a 1024-bit PROM from the early 1970s, programmed once by blowing fuses.
Data is stored in a 33×33 array of diodes and fuses; intact fuses represent 1, blown fuses represent 0.
Address decoding splits into column selection (A3-A7) and output selection (A0-A2) to access 256 4-bit words.

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