Can you design a chip: The protocol emulator ASIC competition
4 days ago
- Design an open-source, general-purpose protocol emulator ASIC that can emulate hardware protocols like UART, SPI, and I2C via a reprogrammable instruction set.
- The chip should be flexible enough to support new protocols post-fabrication, with stretch goals including low-speed USB, 10Mbit Ethernet, JTAG, SWD, PS/2, and CAN bus.
- Target the IHP 130nm CMOS5L process via Tiny Tapeout, using a 6x4 tile area (about 0.7 mm²) with approximately 1K logic cells per tile.
- Submission must be open source, designed for fabrication, and due by January 18, 2027; winners receive fabricated chips on dev boards.
- Emphasize verification techniques, including formal methods, constrained random tests, and AI-assisted verification, as AI-assisted chip design becomes more common.
- Use the provided Verilog template from Tiny Tapeout, run synthesis early, and check timing to ensure routability and speed.