The Scourge of x86 Emulation
5 hours ago
- Emulating x86-TSO memory model on ARM's weak consistency model causes significant performance issues, especially with unaligned accesses and atomic instructions.
- Initial ARMv8.0 workaround using load-acquire/store-release instructions leads to major slowdowns, with some CPUs seeing 50-70% performance penalties for unaligned accesses.
- LRCPC extensions (ARMv8.3+) improve aligned memory performance but fail for unaligned accesses crossing 16-byte granules, requiring expensive DMB backpatching.
- Atomic RMW operations map 1:1 from x86 to ARMv8.1-a, but unaligned atomics are 1000x slower on ARM due to split-lock emulation involving kernel signal handling.
- Apple M1's hardware TSO mode eliminates many overheads but still suffers from split-locks across cachelines; Qualcomm Oryon-3 supports coherent cachelines within 64-byte boundaries.
- Split-lock emulation is often incorrect without hardware support; a proposed solution uses a 128-bit CASP instruction straddling cacheline boundaries.
- Uncached (write-combine) memory performance on ARM is dire, with store bandwidth up to 816x worse than x86, causing games like Hollow Knight to run below 1 FPS.
- UMA systems can bypass uncached memory issues by using cached buffers, but PCIe GPU setups remain problematic, requiring future extensions like FEAT_LRCPC4.
- Vendors are gradually improving hardware support for x86 emulation, but full parity with x86 may require further architectural changes.