Reverse Engineering an ASIC
21 days ago
- A GDS file describes chip layout; the manufacturing process (SkyWater 130 nm) must be identified to interpret layers.
- Standard cell names (e.g., sky130_fd_sc_hd__) reveal logic gate functions; netlist is extracted by tracing conducting paths.
- Simulation of the circuit matches the provided example inputs, producing 'TRY AGAIN' output.
- The chip is divided into 11 regions based on physical location; each region's function is inferred through analysis.
- Region functions include column counter, row counter, patch map, column count, row check, patch count, neighbor check, total count, and success bit.
- Success conditions require exactly two ones per row, per column, per patch, no touching ones, and 22 total ones — the rules of Star Battle.
- The chip acts as a Star Battle validator; the input that makes 'success' high is a valid Star Battle solution.