AMD Takes the Lid Off of Next-Gen EPYC 9006 Venice as Zen 6 Comes to Servers
a day ago
- AMD is launching the EPYC 9006 family of server CPUs based on Zen 6 architecture, built on TSMC 2nm process.
- Two CCD variants: high-performance Zen 6 (up to 96 cores) and dense Zen 6c (up to 256 cores), with L3 cache up to 1024MB.
- New I/O die supports 16 memory channels, DDR5 up to 8000 MT/s and MRDIMMs up to 12,800 MT/s, plus PCIe Gen6 and CXL 3.1.
- Dual IOD design for high-end chips enables tighter cache-coherent coupling with AMD GPUs via unified xGMI.
- Maximum TDP reaches 600W for dense Venice chips, with improved performance-per-watt over Turin.
- The platform also debuts Helios rackscale system and sets the stage for an AI-focused EPYC with LPDDR support in 2027.