3 months ago
- Asymmetric thread fences optimize concurrency by shifting heavy synchronization costs from a common path to an infrequent slow path, using lightweight compiler barriers on the fast path and stronger fences on the slow path.
- The lightweight fence (asymmetric_thread_fence_light) is implemented as a compiler barrier (e.g., asm volatile("" : : : "memory")), preventing compiler reordering but not hardware reordering.
- The heavy fence (asymmetric_thread_fence_heavy) on Linux uses the membarrier() system call, which issues inter-processor interrupts (IPIs) to enforce memory ordering across cores, involving smp_mb() barriers before and after IPI sending.
- The C++ standard formalizes asymmetric fences (P1202R5) by integrating them into the memory model, with rules affecting the single total order S for memory_order_seq_cst operations and requiring careful handling to avoid transitivity issues.
- Implementation details include fast-path optimizations in membarrier() for single-core or single-mm scenarios, architecture-specific smp_mb() implementations, and considerations for data races and happens-before relationships.