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World's Cheapest ARM Debugger is Actually RISC-V
2 months ago
- Author built an ARM debugger using a 10¢ RISC-V ch32v003 microcontroller and free components from disposable vapes.
- Project motivated by a community bounty and desire for simpler, hardware-focused embedded work using C and minimal libraries.
- ch32v003's low-speed USB (rv003usb) limits to interrupt endpoints, but CMSIS-DAP V1 spec supports them.
- Ported DAPLink to ch32fun and rv003usb; probe recognized by pyOCD on macOS after fixing a bit masking bug in PIN_SWDIO_OUT.
- pyOCD works with libhid on macOS but has issues with libusb on Linux; openocd works on Linux after compiling from source.
- Author praises SWD protocol simplicity and the supportive RISC-V community around WCH microcontrollers.
SEAM-V: A Hybrid-Decoupled RISC-V Vector Processor
2 months ago
- The paper introduces SEAM-V, a hybrid-decoupled RISC-V vector execution architecture designed to address limitations in tightly coupled vector implementations.
- SEAM-V uses task-level decoupling, local instruction supply, and VLIW-style packing to form continuous streams of execute packets (EPs), improving instruction supply and reducing scalar-side delays.
- EP identity and request-bound prefetch context remain visible to the dynamic vector backend, enabling same-EP hazard suppression and request-bound prefetching to enhance sustained throughput.
- The architecture supports limited cross-EP vector overlap under safety conditions, while cross-EP dependences, resource conflicts, and memory ordering are dynamically managed by the backend.
- Cycle-accurate RTL evaluation shows SEAM-V achieves a geometric-mean speedup of 1.34x over an Ara-based tightly coupled implementation across 17 kernels, with speedups of 1.50x, 1.25x, and 1.27x for variable-AVL, BLAS/matrix, and fixed-size application groups, respectively.
- At AVL=32, the geometric-mean speedup across six one-dimensional vector kernels approaches 3x.
Milk-V Jupiter2: RVA23-Compliant RISC-V SBC
2 months ago
- First RVA23-compliant RISC-V SBC with RVV 1.0 and 1024-bit vector acceleration.
- 8-core X100 CPU at 2.4GHz and 8-core A100 AI CPU with up to 60 TOPS.
- Up to 32GB LPDDR5, 256GB UFS, and M.2 NVMe storage.
- Networking includes 10GbE SFP+, GbE RJ45, Wi-Fi 6/BT 5.2, and 4G/5G support.
- Dual display outputs: USB-C DP Alt (4K@60Hz) and eDP (2.5K@90Hz).
- Supports multiple OS: Bianbu, Ubuntu, OpenHarmony, OpenKylin, Deepin, Fedora.
Book: RISC-V System-on-Chip Design
3 months ago
- RISC-V System-on-Chip Design is accessible to advanced undergraduates with limited background, covering concepts from operating systems, VLSI, and memory systems.
- It features easy-to-read explanations, sidebars, and humor, similar to Harris and Harris's textbooks, and includes open-source SystemVerilog code, validation code, and benchmarking tools.
- The book provides detailed design for microprocessor components, implementation of RISC-V microprocessors, and enables building processors on the open-source Skywater process.
- Authors James Stine and Sarah L. Harris are experts in computer arithmetic, VLSI, and digital circuit design, with backgrounds at institutions like Oklahoma State University and Harvey Mudd College.
- Published by Morgan Kaufmann in July 2026, it has 856 pages, ISBN-10: 0323994989, and ranks in categories like Integrated Circuits and Computer Hardware Design.
Modder builds 8,192-core GPU at home out of RISC-V microcontrollers
3 months ago
- A modder built an 8,192-core GPU from RISC-V microcontrollers, each with an RGB LED, creating a combined graphics card and monitor.
- The project uses 8,192 chips (planned for 64,000 for 320x200 resolution), draws over 2,000 watts of power, and requires a custom 3D-printed tool for programming.
- Each microcontroller costs $0.13, leading to over $8,000 for the full array, with power supplied via a Corsair WS3000 PSU and custom converters.
- The design features custom six-layer PCBs in a circular arrangement, inspired by the Cray-1, and addresses challenges like cooling and high-current power delivery.
One man, two kernels, and a lot of RISC-V
3 months ago
- Yuri Zaporozhets develops multiple projects, including a RISC-V-based GateMate PC inspired by IBM PS/2, a System/359 mini-mainframe on FPGA, and ports/rewrites of QNX.
- He ported QNX 6.4 to RISC-V as QRV, later creating QSOE with two variants: one on the Skimmer microkernel and another on seL4, both under Apache 2.0 license.
- Zaporozhets uses AI tools like Claude LLM but has long-standing expertise, dating back to projects like RadiOS in 2003, focusing on open-source, low-level systems design.
Pine64 launch $50 smart speaker for Home Assistant tinkerers
3 months ago
- Pine64 launched PineVoice, a $50 smart speaker with RISC-V chip and open-source software.
- Hardware includes Bouffalo Lab BL606P SoC with Wi-Fi, Bluetooth 5.0, Zigbee, dual mics, speaker, and local wake word detection.
- Factory firmware uses Alibaba's YoC platform and Wyoming Satellite protocol for Linux-based Home Assistant, though Wyoming is deprecated.
- Specs: 32 MiB pSRAM, 16 MiB flash, 128 KiB ROM; intended as embedded device, not high-performance PC.
- Early-stage development; may have quirks; firmware updates expected; not a consumer-grade product.
- Pine64 focuses on low-cost, open hardware for developers; comparable price to Amazon Echo Dot and Google Nest Mini.
- Unlike cloud-dependent proprietary devices, PineVoice targets local, open-source networks.
- Available for $49.99 with USB cable, guide, 30-day warranty; suitable for tinkerers.

risc-v

World's Cheapest ARM Debugger is Actually RISC-V

SEAM-V: A Hybrid-Decoupled RISC-V Vector Processor

Milk-V Jupiter2: RVA23-Compliant RISC-V SBC

Book: RISC-V System-on-Chip Design

Modder builds 8,192-core GPU at home out of RISC-V microcontrollers

One man, two kernels, and a lot of RISC-V

Pine64 launch $50 smart speaker for Home Assistant tinkerers