- The paper introduces SEAM-V, a hybrid-decoupled RISC-V vector execution architecture designed to address limitations in tightly coupled vector implementations.
- SEAM-V uses task-level decoupling, local instruction supply, and VLIW-style packing to form continuous streams of execute packets (EPs), improving instruction supply and reducing scalar-side delays.
- EP identity and request-bound prefetch context remain visible to the dynamic vector backend, enabling same-EP hazard suppression and request-bound prefetching to enhance sustained throughput.
- The architecture supports limited cross-EP vector overlap under safety conditions, while cross-EP dependences, resource conflicts, and memory ordering are dynamically managed by the backend.
- Cycle-accurate RTL evaluation shows SEAM-V achieves a geometric-mean speedup of 1.34x over an Ara-based tightly coupled implementation across 17 kernels, with speedups of 1.50x, 1.25x, and 1.27x for variable-AVL, BLAS/matrix, and fixed-size application groups, respectively.
- At AVL=32, the geometric-mean speedup across six one-dimensional vector kernels approaches 3x.