Instruction decoding in the Intel 8087 floating-point chip
12 hours ago
- The 8087 coprocessor determines if an instruction is for it by watching the 8086/8088's bus for ESCAPE opcodes, using its Bus Interface Unit to duplicate the CPU's instruction queue.
- Instruction decoding inside the 8087 involves multiple layers: a decoding PLA maps instruction bits to 22 microcode entry points, with additional pre-processing to reduce PLA size.
- Many instructions share microcode routines, with conditional jumps (based on 49 conditions) enabling different paths for operations like addition vs. subtraction.
- Some instructions (e.g., interrupt control or state save/restore) are implemented directly in hardware by the BIU, using small PLAs and logic gates, and may switch to microcode for floating-point register operations.
- The 8087's constant-loading instructions use three separate decoding mechanisms: the instruction decode ROM selects the microcode routine, a constant PLA selects the constant, and microcode tests the instruction's bottom bit to adjust the exponent.