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Notes on the Pentium's microcode circuitry
13 hours ago
- Microcode is a layer of software underneath machine instructions, implemented as micro-instructions stored in a ROM.
- The Pentium's microcode ROM has 4608 micro-instructions, each 90 bits wide, stored in two banks with 288 rows and 720 columns each.
- Bits are stored via the presence or absence of NMOS transistors in a grid, with transistors pulling output lines low.
- The Microcode Address Register (MAR) holds 13-bit addresses to select rows and columns in the ROM, supporting increment, branch, and subroutine calls with up to three levels of stack.
- Row-select drivers use optimized decoders with 6-input AND gates and 3-bit decoding to activate one of 288 rows efficiently.
- Output circuitry includes multiplexers to select one of 16 columns per bit, followed by latches and BiCMOS drivers for amplification.
- Testing circuitry uses linear feedback shift registers (LFSRs) to scan the ROM and compute checksums, enabling detection of single-bit errors.
- The ROM's complexity arises from optimized layout (e.g., mirrored column groups, BiCMOS drivers) and testability features.
Notes on the Intel 8086 processor's arithmetic-logic unit
13 hours ago
- Intel introduced the 8086 processor in 1978, a 16-bit chip that founded the x86 architecture.
- The ALU performs 28 operations including arithmetic, logic, shifts, and BCD adjustments.
- Microcode controls the ALU via a two-step process: first configure the ALU, then retrieve the result.
- The ALU uses a lookup table approach with six control signals to implement various operations.
- The die photo shows the chip partitioned into Bus Interface Unit (BIU) and Execution Unit (EU), with ALU control circuitry highlighted.
- The ALU control circuitry includes latches, PLAs, multiplexers, and flip-flops to decode micro-instructions and instruction opcodes.
- The XI pseudo-operation allows the same microcode to handle multiple machine instructions by substituting the ALU operation from the opcode.
- The 8086's CISC design introduces complexity through special cases like shifts, decimal adjustments, and carry handling.
Instruction decoding in the Intel 8087 floating-point chip
13 hours ago
- The 8087 coprocessor determines if an instruction is for it by watching the 8086/8088's bus for ESCAPE opcodes, using its Bus Interface Unit to duplicate the CPU's instruction queue.
- Instruction decoding inside the 8087 involves multiple layers: a decoding PLA maps instruction bits to 22 microcode entry points, with additional pre-processing to reduce PLA size.
- Many instructions share microcode routines, with conditional jumps (based on 49 conditions) enabling different paths for operations like addition vs. subtraction.
- Some instructions (e.g., interrupt control or state save/restore) are implemented directly in hardware by the BIU, using small PLAs and logic gates, and may switch to microcode for floating-point register operations.
- The 8087's constant-loading instructions use three separate decoding mechanisms: the instruction decode ROM selects the microcode routine, a constant PLA selects the constant, and microcode tests the instruction's bottom bit to adjust the exponent.

microcode

Notes on the Pentium's microcode circuitry

Notes on the Intel 8086 processor's arithmetic-logic unit

Instruction decoding in the Intel 8087 floating-point chip