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TIRx: An Open Compiler Stack for Evolving Frontier ML Kernels
6 days ago
- TIRx is an open-source, hardware-native DSL and compiler for ML kernels built on Apache TVM, targeting GPUs and specialized AI accelerators.
- It provides a low-level boundary that keeps orchestration, synchronization, and backend intrinsics in source code for expert control.
- Recurring tile primitives are exposed to the compiler for reusability across kernels and backends.
- New hardware support is introduced first as intrinsics, then promoted to tile primitives as patterns stabilize.
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Fleet: Hierarchical Task-Based Abstraction for Megakernels on Multi-Die GPUs
17 days ago
- Fleet is a multi-level task model for multi-die GPUs, introducing Chiplet-tasks to bind work and data to a chiplet for better locality and synchronization.
- It addresses the mismatch between flat GPU programming models (CUDA/HIP) and chiplet-based designs, reducing redundant memory traffic and improving cache utilization.
- On AMD Instinct MI350 with Qwen3-8B, Fleet lowers decode latency by 1.3-1.5x at small batch sizes and achieves up to 1.30x speedup at larger batches via cooperative weight tiling and increased L2 hit rates.
Show HN: Phobos – A tiny scale-free kernel language with tile-DAG support
a month ago
- The author developed Phobos, a tiny kernel language inspired by Triton that compiles to PTX and runs on NVIDIA GPUs.
- Phobos achieves about 76% of cuBLAS SGEMM performance on an RTX 2080 SUPER, with optimizations like tiling and tensor core usage.
- The language abstracts thread-level details, focusing on tile-level operations for AI computations, enabling natural scaling to distributed clusters.
- The project involved learning low-level GPU programming, using MLIR and LLVM with Rust, and implementing autotuning for kernel parameters.
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Matrix Multiplication on Blackwell
a month ago
- Matrix multiplication (matmul) is a core operation for LLMs, with over 83% of runtime in models like Llama 8B spent on matmul variants.
- GPUs offer massive parallelism (e.g., B200 handles up to 151,552 threads) and dedicated tensor cores for efficient matmul via MMA operations.
- Blackwell GPUs introduce 5th-gen tensor cores (tcgen05) supporting 256x256x16 MMA, tensor memory for reduced register usage, and enhanced pipelining.
- GPU programming uses a SIMT model where threads compute elements in parallel, organized into warps, blocks (CTAs), and clusters for memory sharing.
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gpu programming

TIRx: An Open Compiler Stack for Evolving Frontier ML Kernels

Fleet: Hierarchical Task-Based Abstraction for Megakernels on Multi-Die GPUs

Show HN: Phobos – A tiny scale-free kernel language with tile-DAG support

Matrix Multiplication on Blackwell